Remote Powering and Data Communication for Implanted Biomedical Systems by Enver Gurhan Kilinc Catherine Dehollain & Franco Maloberti

Author:Enver Gurhan Kilinc, Catherine Dehollain & Franco Maloberti
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

The reference voltage generation circuit with start-up is fabricated in 0.18  m CMOS process. Figure 3.42 shows the micrograph of the fabricated reference generation with circuit start-up. The reference generation circuit is designed to create 0.9 V reference voltage () and has power supply rejection (PSRR) response of 78.6 dB at DC and 47.8 dB at 27.12 MHz in post-layout simulation.

Fig. 3.42Micrograph of fabricated reference generation circuit with start-up

3.3.4 Power on Reset

The power level at the implantable system should be monitored and the implantable circuits such as sensor interface, microprocessor, data communication, etc. should be disabled to prevent redundant current consumption. When the remote powering is turned on, the power level at the implantable system is initially zero. Therefore, the implantable system needs to accupmulate charge on the capacitor to reach sufficient voltage level for the bio-sensor system. However, all circuits draw current from the capacitor which increase the duration to reach the proper operation. A power-on-reset (PoR) circuit is required to disable the circuits until the capacitor is charged to a certain voltage level. In addition, the charge on the capacitor is saved by deactivating the circuits if the regulator voltage (V reg ) drops under a certain voltage. Accordingly, the inappropriate current consumption by the circuits is avoided.

On the other hand, the digital circuits have malfunctions and/or failures when the circuits are initiated at the insufficient voltage level. In order to prevent these issues due to an insufficient supply voltage, a PoR circuit is needed to send “RESET” command to the digital circuits. The level of V reg is tracked by the PoR circuit [73]. The PoR circuit sends “power-up” signal and enables all circuits when the supply voltage is high enough. In addition, the PoR disables all chip and sends “power-down” signal when V reg voltage level decreases under a certain level where the circuits perform improperly.

Figure 3.43 shows the circuit schematic of Power on Reset. When V reg supply voltage increases, the current and voltage of M 1 transistor increases. The increase on voltage is delayed by charging the C 1 capacitance. When voltage reaches to threshold voltage of M 2 transistor, M 2 transistor turns on and N times current of M 1 transistor starts to flow over M 2 transistor. Accordingly, the drain voltage of M 2 transistor decreases and is tracked by M 8 transistor. Transistor M 8 produces a positive feedback which increases voltage that also increases the drain current of M 2. Accordingly, the gate voltage of M 3 decreases under threshold voltage of M 3 and finally M 3 turns off at a certain V reg voltage level. Therefore, the input of the inverter converges to V reg voltage and “power-up” signal is supplied to enable all circuits. The inverter is used to obtain rail-to-rail signal. On the other hand, “power-down” signal is created to disable the circuits by the same mechanism which is performed reversely while V reg voltage decreases.

Fig. 3.43Circuit schematic of Power-on-Reset (PoR)

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